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fix arm thread-pointer/atomic asm when compiling to thumb code

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armv7/thumb2 provides a way to do atomics in thumb mode, but for armv6
we need a call to arm mode.

this commit is based on a patch by Stephen Thomas which fixed the
armv7 cases but not the armv6 ones.

all of this should be revisited if/when runtime selection of thread
pointer access and atomics are added.
This commit is contained in:
Rich Felker
2014-04-30 15:32:11 -04:00
parent 468bc11ed0
commit e783efa6ef
2 changed files with 7 additions and 6 deletions
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arch/arm/atomic.h
+5 -3
View File
@@ -22,9 +22,8 @@ static inline int a_ctz_64(uint64_t x)
return a_ctz_l(y);
}
#if __ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6ZK__ \
|| __ARM_ARCH_7A__ || __ARM_ARCH_7R__ \
|| __ARM_ARCH >= 7
#if ((__ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6ZK__) && !__thumb__) \
|| __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
#if __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
#define MEM_BARRIER "dmb ish"
@@ -39,6 +38,9 @@ static inline int __k_cas(int t, int s, volatile int *p)
" " MEM_BARRIER "\n"
"1: ldrex %0,%3\n"
" subs %0,%0,%1\n"
#ifdef __thumb__
" itt eq\n"
#endif
" strexeq %0,%2,%3\n"
" teqeq %0,#1\n"
" beq 1b\n"
arch/arm/pthread_arch.h
+2 -3
View File
@@ -1,6 +1,5 @@
#if __ARM_ARCH_6K__ || __ARM_ARCH_6ZK__ \
|| __ARM_ARCH_7A__ || __ARM_ARCH_7R__ \
|| __ARM_ARCH >= 7
#if ((__ARM_ARCH_6K__ || __ARM_ARCH_6ZK__) && !__thumb__) \
|| __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
static inline __attribute__((const)) pthread_t __pthread_self()
{